An approach to reduce computational cost in combinatorial logic netlist reliability analysis using circuit clustering and conditional probabilities

Josep Torras Flaquer, Jean-Marc Daveau, Lirida A. B. Naviner, Philippe Roche. An approach to reduce computational cost in combinatorial logic netlist reliability analysis using circuit clustering and conditional probabilities. In 17th IEEE International On-Line Testing Symposium (IOLTS 2011), 13-15 July, 2011, Athens, Greece. pages 98-103, IEEE, 2011. [doi]

Authors

Josep Torras Flaquer

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Jean-Marc Daveau

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Lirida A. B. Naviner

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Philippe Roche

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