Eric J. Fluhr, Steve Baumgartner, David W. Boerstler, John F. Bulzacchelli, Timothy Diemoz, Daniel Dreps, George English, Joshua Friedrich, Anne Gattiker, Tilman Gloekler, Christopher Gonzalez, Jason Hibbeler, Keith A. Jenkins, Yong Kim, Paul Muench, Ryan Nett, Jose Paredes, Juergen Pille, Donald W. Plass, Phillip Restle, Raphael Robertazzi, David Shan, David W. Siljenberg, Michael Sperling, Kevin G. Stawiasz, Gregory Still, Zeynep Toprak Deniz, James D. Warnock, Glen A. Wiedemeier, Victor V. Zyuban. The 12-Core POWER8™ Processor With 7.6 Tb/s IO Bandwidth, Integrated Voltage Regulation, and Resonant Clocking. J. Solid-State Circuits, 50(1):10-23, 2015. [doi]
@article{FluhrBBBDDEFGGGHJKMNPPPRRSSSSSDWWZ15,
title = {The 12-Core POWER8™ Processor With 7.6 Tb/s IO Bandwidth, Integrated Voltage Regulation, and Resonant Clocking},
author = {Eric J. Fluhr and Steve Baumgartner and David W. Boerstler and John F. Bulzacchelli and Timothy Diemoz and Daniel Dreps and George English and Joshua Friedrich and Anne Gattiker and Tilman Gloekler and Christopher Gonzalez and Jason Hibbeler and Keith A. Jenkins and Yong Kim and Paul Muench and Ryan Nett and Jose Paredes and Juergen Pille and Donald W. Plass and Phillip Restle and Raphael Robertazzi and David Shan and David W. Siljenberg and Michael Sperling and Kevin G. Stawiasz and Gregory Still and Zeynep Toprak Deniz and James D. Warnock and Glen A. Wiedemeier and Victor V. Zyuban},
year = {2015},
doi = {10.1109/JSSC.2014.2358553},
url = {http://dx.doi.org/10.1109/JSSC.2014.2358553},
researchr = {https://researchr.org/publication/FluhrBBBDDEFGGGHJKMNPPPRRSSSSSDWWZ15},
cites = {0},
citedby = {0},
journal = {J. Solid-State Circuits},
volume = {50},
number = {1},
pages = {10-23},
}