The following publications are possibly variants of this publication:
- VLSI Implementation of a Fault-Tolerant Distributed Clock GenerationM. Ferringer, G. Fuchs, A. Steininger, G. Kempf. dft 2006: 563-571 [doi]
- VLSI Implementation of a Distributed Algorithm for Fault-Tolerant Clock GenerationGottfried Fuchs, Andreas Steininger. jece, 2011, 2011. [doi]
- Brief announcement: how to speed-up fault-tolerant clock generation in VLSI systems-on-chip via pipeliningAndreas Dielacher, Matthias Függer, Ulrich Schmid. podc 2009: 276-277 [doi]
- How to Speed-Up Fault-Tolerant Clock Generation in VLSI Systems-on-Chip via PipeliningMatthias Függer, Andreas Dielacher, Ulrich Schmid. edcc 2010: 230-239 [doi]