The following publications are possibly variants of this publication:
- Test set embedding for deterministic BIST using a reconfigurable interconnection networkLei Li, Krishnendu Chakrabarty. tcad, 23(9):1289-1305, 2004. [doi]
- A Reconfigurable Scan Architecture With Weighted Scan-Enable Signals for Deterministic BISTDong Xiang, Yang Zhao, Krishnendu Chakrabarty, Hideo Fujiwara. tcad, 27(6):999-1012, 2008. [doi]
- Column Scan Optimization by Increasing Intra-Instruction ParallelismNusrat Jahan Lisa, Annett Ungethüm, Dirk Habich, Tuan D. A. Nguyen, Akash Kumar 0001, Wolfgang Lehner. QIMIE 2018: 344-353 [doi]