The following publications are possibly variants of this publication:
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- On the need for a new ESD verification methodology to improve the reliability of ICs in advanced 28nm UTBB FD-SOI technologyB. Viale, M. Fer, L. Courau, Philippe Galy, Bruno Allard. mr, 64:101-108, 2016. [doi]
- Preliminary results on TFET - Gated diode in thin silicon film for IO design & ESD protection in 28nm UTBB FD-SOI CMOS technologyPhilippe Galy, S. Athanasiou. icicdt 2016: 1-4 [doi]
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