Circuit Topology-Based Test Pattern Generation for Small-Delay Defects

Sandeep Kumar Goel, Krishnendu Chakrabarty. Circuit Topology-Based Test Pattern Generation for Small-Delay Defects. In Sandeep Kumar Goel, Krishnendu Chakrabarty, editors, Testing for Small-Delay Defects in Nanoscale CMOS Integrated Circuits. pages 161-184, CRC Press, 2014.

@incollection{GoelC14,
  title = {Circuit Topology-Based Test Pattern Generation for Small-Delay Defects},
  author = {Sandeep Kumar Goel and Krishnendu Chakrabarty},
  year = {2014},
  researchr = {https://researchr.org/publication/GoelC14},
  cites = {0},
  citedby = {0},
  pages = {161-184},
  booktitle = {Testing for Small-Delay Defects in Nanoscale CMOS Integrated Circuits},
  editor = {Sandeep Kumar Goel and Krishnendu Chakrabarty},
  publisher = {CRC Press},
  isbn = {978-1-439-82941-7},
}