Circuit Topology-Based Test Pattern Generation for Small-Delay Defects

Sandeep Kumar Goel, Krishnendu Chakrabarty. Circuit Topology-Based Test Pattern Generation for Small-Delay Defects. In Sandeep Kumar Goel, Krishnendu Chakrabarty, editors, Testing for Small-Delay Defects in Nanoscale CMOS Integrated Circuits. pages 161-184, CRC Press, 2014.

References

No references recorded for this publication.

Cited by

No citations of this publication recorded.