A 64×32bit 4-read 2-write low power and area efficient register file in 65nm CMOS - researchr publication authors

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Jun Han, Xingxing Zhang, Yi Li, Baoyu Xiong, Yuejun Zhang, Zhang Zhang, Zhiyi Yu, Jun Han, Xu Cheng, Xiaoyang Zeng. A 64×32bit 4-read 2-write low power and area efficient register file in 65nm CMOS. IEICE Electronic Express, 9(16):1355-1361, 2012. [doi]

This author has not been identified. Look up 'Jun Han' in GoogleThis author has not been identified. Look up 'Xingxing Zhang' in GoogleThis author has not been identified. Look up 'Yi Li' in GoogleThis author has not been identified. Look up 'Baoyu Xiong' in GoogleThis author has not been identified. Look up 'Yuejun Zhang' in GoogleThis author has not been identified. Look up 'Zhang Zhang' in GoogleThis author has not been identified. Look up 'Zhiyi Yu' in GoogleThis author has not been identified. Look up 'Jun Han' in GoogleThis author has not been identified. Look up 'Xu Cheng' in GoogleThis author has not been identified. Look up 'Xiaoyang Zeng' in Google

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