Post-layout transistor sizing for power reduction in cell-based design - researchr publication authors

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Masanori Hashimoto, Hidetoshi Onodera. Post-layout transistor sizing for power reduction in cell-based design. In Proceedings of ASP-DAC 2001, Asia and South Pacific Design Automation Conference 2001, January 30-February 2, 2001, Yokohama, Japan. pages 359-365, ACM, 2001. [doi]

This author has not been identified. Look up 'Masanori Hashimoto' in GoogleThis author has not been identified. Look up 'Hidetoshi Onodera' in Google

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