Masanori Hashimoto, Hidetoshi Onodera. Post-layout transistor sizing for power reduction in cell-based design. In Proceedings of ASP-DAC 2001, Asia and South Pacific Design Automation Conference 2001, January 30-February 2, 2001, Yokohama, Japan. pages 359-365, ACM, 2001. [doi]
@inproceedings{HashimotoO01:0,
title = {Post-layout transistor sizing for power reduction in cell-based design},
author = {Masanori Hashimoto and Hidetoshi Onodera},
year = {2001},
doi = {10.1145/370155.370392},
url = {http://doi.acm.org/10.1145/370155.370392},
tags = {rule-based, layout, design},
researchr = {https://researchr.org/publication/HashimotoO01%3A0},
cites = {0},
citedby = {0},
pages = {359-365},
booktitle = {Proceedings of ASP-DAC 2001, Asia and South Pacific Design Automation Conference 2001, January 30-February 2, 2001, Yokohama, Japan},
publisher = {ACM},
isbn = {0-7803-6634-4},
}