Toshinori Hosokawa, Hiroshi Date, Michiaki Muraoka. A Test Generation Method Using a Compacted Test Table and a Test Generation Method Using a Compacted Test Plan Table for RTL Data Path Circuits. In 20th IEEE VLSI Test Symposium (VTS 2002), Without Testing It s a Gamble, 28 April - 2 May 2002, Monterey, CA, USA. pages 328-335, IEEE Computer Society, 2002. [doi]
@inproceedings{HosokawaDM02:0,
title = {A Test Generation Method Using a Compacted Test Table and a Test Generation Method Using a Compacted Test Plan Table for RTL Data Path Circuits},
author = {Toshinori Hosokawa and Hiroshi Date and Michiaki Muraoka},
year = {2002},
url = {http://csdl.computer.org/comp/proceedings/vts/2002/1570/00/15700328abs.htm},
tags = {testing},
researchr = {https://researchr.org/publication/HosokawaDM02%3A0},
cites = {0},
citedby = {0},
pages = {328-335},
booktitle = {20th IEEE VLSI Test Symposium (VTS 2002), Without Testing It s a Gamble, 28 April - 2 May 2002, Monterey, CA, USA},
publisher = {IEEE Computer Society},
isbn = {0-7695-1570-3},
}