The following publications are possibly variants of this publication:
- A Simulator for Evaluating Redundancy Analysis Algorithms of Repairable Embedded MemoriesRei-Fu Huang, Jin-Fu Li, Jen-Chieh Yeh, Cheng-Wen Wu. mtdt 2002: 68 [doi]
- Efficient built-in redundancy analysis for embedded memories with 2-D redundancyShyue-Kung Lu, Yu-Chen Tsai, Chih-Hsien Hsu, Kuo-Hua Wang, Cheng-Wen Wu. tvlsi, 14(1):34-42, 2006. [doi]
- A Built-In Self-Repair Scheme for Semiconductor Memories with 2-D RedundancyJin-Fu Li, Jen-Chieh Yeh, Rei-Fu Huang, Cheng-Wen Wu, Peir-Yuan Tsai, Archer Hsu, Eugene Chow. itc 2003: 393-402 [doi]
- A Built-In Redundancy-Analysis Scheme for Self-Repairable RAMs with Two-Level RedundancyYu-Jen Huang, Da-Ming Chang, Jin-Fu Li. dft 2006: 362-370 [doi]