Table of Contents

• An Architecture for Self-Healing Digital SystemsParag K. Lala, B. Kiran Kumar. 3-7 [doi]
• Coding Scheme for Low Energy Consumption Fault-Tolerant BusDaniele Rossi, Steven V. E. S. van Dijk, Richard P. Kleihorst, A. H. Nieuwland, Cecilia Metra. 8-12 [doi]
• Survivable Discrete Circuits DesignA. Matrosova, V. Andreeva, Yu. Sedov. 13 [doi]
• Fault Tolerance Evaluation Using Two Software Based Fault Injection MethodsAstrit Ademaj, Petr Grillinger, Pavel Herout, Jan Hlavicka. 21-25 [doi]
• Automated Synthesis of SEU Tolerant Architectures from OO DescriptionsSilvia Chiusano, Stefano Di Carlo, Paolo Prinetto. 26-31 [doi]
• A System Level Approach in Designing Dual-Duplex Fault Tolerant Embedded SystemsCristiana Bolchini, Luigi Pomante, Fabio Salice, Donatella Sciuto. 32 [doi]
• A New Self-Checking Code-Disjoint Carry-Skip AdderDaniel Marienfeld, Egor S. Sogomonyan, Vitalij Ocheretnij, Michael Gössel. 39-43 [doi]
• Sequential Circuits Applicable for Detecting Different Types of FaultsIlya Levin, Vladimir Sinelnikov, Mark G. Karpovsky, Sergey Ostanin. 44 [doi]
• A High Speed Encoder for Recursive Systematic Convolutive CodesAmine M sir, Fabrice Monteiro, Abbas Dandache, Bernard Lepley. 51-55 [doi]
• A Hierarchical Architecture for Concurrent Soft Error Detection Based on Current SensingY. Tsiatouhas, Angela Arapoyanni, Dimitris Nikolos, Th. Haniotakis. 56-60 [doi]
• Design of Real-Number Checksum Codes Using Shared Partial Computation for CED in Linear DSP SystemsHuy Nguyen, Abhijit Chatterjee. 61 [doi]
• On-Line Error Detection and Correction in Storage Elements with Cross-Parity CheckMatthias Pflanz, K. Walther, Christian Galke, Heinrich Theodor Vierhaus. 69-73 [doi]
• On-Line Monitor Design of Finite-State MachinesFeng Gao, John P. Hayes. 74-78 [doi]
• A Statistical Sampler for a New On-line Analog Test MethodMarcelo Negreiros, Luigi Carro, Altamiro Amadeu Susin. 79 [doi]
• A BICS for CMOS Opamps by Monitoring the Supply Current PeakJoan Font, J. Ginard, Eugeni Isern, Miquel Roca, Jaume Segura, Eugenio García. 94-98 [doi]
• Analog Switches in Programmable Analog Devices: Quiescent Defective BehavioursRosa Rodríguez-Montañés, D. Muñoz, L. Balado, Joan Figueras. 99-103 [doi]
• Multi-Level Fault Injection Experiments Based on VHDL Descriptions: A Case StudyRégis Leveugle, K. Hadjiat. 107-111 [doi]
• Analysis of SEU Effects in a Pipelined ProcessorMaurizio Rebaudengo, Matteo Sonza Reorda, Massimo Violante. 112-116 [doi]
• Bit Flip Injection in Processor-Based Architectures: A Case StudyGian-Carlo Cardarilli, F. Kaddour, A. Leandri, Marco Ottavi, Salvatore Pontarelli, Raoul Velazco. 117 [doi]
• BIST-Based Delay-Fault Testing in FPGAsMiron Abramovici, Charles E. Stroud. 131-134 [doi]
• Built-In-Self-Test of Analogue Circuits Using Optimised Fault Sets and Transient Response TestingN. Axelos, J. Watson, D. Taylor, A. Platts. 135-139 [doi]
• A Low Power Pseudo-Random BIST TechniqueNadir Z. Basturkmen, Sudhakar M. Reddy, Irith Pomeranz. 140 [doi]
• Stop & Go BISTIlia Polian, Bernd Becker. 147-151 [doi]
• Bit-Serial Test Pattern Generation by an Accumulator Behaving as a Non-Linear Feedback Shift RegisterGiorgos Dimitrakopoulos, Dimitris Nikolos, Dimitris Bakalis. 152-157 [doi]
• Built-in Generation of m -Sequences with Irreducible Characteristic PolynomialsDimitri Kagaris. 158 [doi]
• Active Replication: Towards a Truly SRAM-Based FPGA On-Line Concurrent TestingManuel G. Gericota, Gustavo R. Alves, Miguel L. Silva, José M. Ferreira. 165-169 [doi]
• Checkers for RF Matching Networks on an Automatic Test BoardGiuseppe Di Gregorio, Maria Grazia La Rosa, Biagio Russo. 170 [doi]
• Adaptive IDDQ: How to Set an IDDQ Limit for any Device Under TestCarlo Dallavalle. 177 [doi]
• On-line Detection and Compensation of Transient Errors in Processor Pipeline-StructuresChristian Galke, Matthias Pflanz, Heinrich Theodor Vierhaus. 178 [doi]
• Recovering Sequential Circuits from Temporary Faults: The Survival Capability of Scan-CellsJose Miguel Vieira dos Santos. 179 [doi]
• Learning-Based On-Line Testing in Feedforward Neural NetworksNaotake Kamiura, Kazuharu Yamato, Teijiro Isokawa, Nobuyuki Matsui. 180 [doi]
• On-Line Detection of Short Circuits in Digital Devices and SystemsAdam Kristof. 183 [doi]
• Using Concurrent and Semi-Concurrent On-Line Testing During HLS: An Adaptable ApproachMohammad A. Naal, M. Rakotoar, Emmanuel Simeu, Chouki Aktouf. 184 [doi]
• Transformation Based Insertion of On-Line Testing Resources in a High-Level Synthesis EnvironmentPetros Oikonomakos, Mark Zwolinski. 185 [doi]
• Robust Data Compression for Analogue Test OutputsAleksandra Rankov, Gaynor E. Taylor, John Webster. 186 [doi]
• A New On-Line Robust Approach to Design Noise Immune Speech Recognition SystemsFabian Vargas, Rubem Dutra Ribeiro Fagundes, Daniel Barros Jr.. 187 [doi]
• Radiation Effects Facility RADEFAri Virtanen. 188 [doi]
• Sequential n -Detection Criteria: Keep It SimpleIlia Polian, Martin Keim, Nicolai Mallig, Bernd Becker. 189 [doi]
• On-line Testing of Embedded Systems Using Optical Probes: System Modeling and Probing TechnologyChouki Aktouf, Benoît Pannetier, Pierre Lemaître-Auger, Smail Tedjini. 191 [doi]
• An Off-Chip Sensor Circuit for On-Line Transient Current TestingB. Alorda, André Ivanov, Jaume Segura. 192 [doi]
• Analysis of the Equivalences and Dominances of Transient Faults at the RT LevelLuis Berrojo, Isabel González, Luis Entrena, Celia López, Fulvio Corno, Matteo Sonza Reorda, Giovanni Squillero. 193 [doi]
• Injecting Multiple Upsets in a SEU Tolerant 8051 Micro-ControllerFernanda Gusmão de Lima, Luigi Carro, Raoul Velazco, Ricardo Augusto da Luz Reis. 194 [doi]
• Error Rate Estimation for a Flight Application Using the CEU Fault Injection ApproachF. Kaddour, Sana Rezgui, Raoul Velazco, S. Rodriguez, J. R. De Mingo. 195 [doi]
• Defect-Oriented Analysis of Memory BIST TestsAlvin Jee. 201-205 [doi]
• A BIST-Based Solution for the Diagnosis of Embedded Memories Adopting Image Processing TechniquesDavide Appello, Alessandra Fudoli, Vincenzo Tancorre, Fulvio Corno, Maurizio Rebaudengo, Matteo Sonza Reorda. 206-210 [doi]
• A Scan-Bist Environment for Testing Embedded MemoriesFarzin Karimi, Fabrizio Lombardi. 211 [doi]
• Fast and Compact Error Correcting Scheme for Reliable Multilevel Flash MemoriesDaniele Rossi, Cecilia Metra, Bruno Riccò. 221-225 [doi]
• High Speed 15 ns 4 Mbits SRAM for Space ApplicationBernard Coloma, Patrick Delaunay, Olivier Husson. 226 [doi]
• The YATE Fail-Safe Interface: The User s Point of ViewD. Bied-Charreton, D. Guillon, B. Jacques. 233 [doi]
• Fault Tolerant Insertion and Verification: A Case StudyAlberto Manzone, Diego De Costantini. 238-242 [doi]
• Design and Implementation of a Self-Checking Scheme for Railway Trackside SystemsLuca Schiano, Cecilia Metra, Diego Marino. 243 [doi]
• A Silicon-Based Yiel Gain Evaluation Methodology for Embedded-SRAMs with Different Redundancy ScenariosEmmanuel Rondey, Yann Tellier, Simone Borri. 251-255 [doi]
• A March-Based Fault Location Algorithm for Static Random Access MemoriesValery A. Vardanian, Yervant Zorian. 256-261 [doi]
• A Simulator for E aluating Redundancy Analysis Algorithms of Repairable Embedded MemoriesRei-Fu Huang, Jin-Fu Li, Jen-Chieh Yeh, Cheng-Wen Wu. 262 [doi]