Manish Kumar Jaiswal, Ray C. C. Cheung. Area-efficient architectures for double precision multiplier on FPGA, with run-time-reconfigurable dual single precision support. Microelectronics Journal, 44(5):421-430, 2013. [doi]
@article{JaiswalC13,
title = {Area-efficient architectures for double precision multiplier on FPGA, with run-time-reconfigurable dual single precision support},
author = {Manish Kumar Jaiswal and Ray C. C. Cheung},
year = {2013},
doi = {10.1016/j.mejo.2013.02.021},
url = {http://dx.doi.org/10.1016/j.mejo.2013.02.021},
researchr = {https://researchr.org/publication/JaiswalC13},
cites = {0},
citedby = {0},
journal = {Microelectronics Journal},
volume = {44},
number = {5},
pages = {421-430},
}