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Manish Kumar Jaiswal, Ray C. C. Cheung. Area-efficient architectures for double precision multiplier on FPGA, with run-time-reconfigurable dual single precision support. Microelectronics Journal, 44(5):421-430, 2013. [doi]
Possibly Related PublicationsThe following publications are possibly variants of this publication: Design of quadruple precision multiplier architectures with SIMD single and double precision supportManish Kumar Jaiswal, Hayden Kwok-Hay So. integration, 65:163-174, 2019. [doi] Dual-mode double precision / two-parallel single precision floating point multiplier architectureManish Kumar Jaiswal, Hayden Kwok-Hay So. vlsi 2015: 213-218 [doi] Area-Efficient Architecture for Dual-Mode Double Precision Floating Point DivisionManish Kumar Jaiswal, Hayden Kwok-Hay So. tcas, 64-I(2):386-398, 2017. [doi] Efficient Implementation of IEEE Double Precision Floating-Point Multiplier on FPGAManish Kumar Jaiswal, Nitin Chandrachoodan. iciis 2008: 1-4 [doi]
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