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Niraj K. Jha. Detecting Multiple Faults in CMOS Circuits. In Proceedings International Test Conference 1986, Washington, D.C., USA, September 1986. pages 514-519, IEEE Computer Society, 1986.
Possibly Related PublicationsThe following publications are possibly variants of this publication: Testing for multiple faults in domino-CMOS logic circuitsNiraj K. Jha. tcad, 7(1):109-116, 1988. [doi] Multiple Input Bridging Fault Detection in CMOS Sequential CircuitsNiraj K. Jha, Sying-Jyan Wang, Phillip C. Gripka. iccd 1992: 369-372 Multiple Stuck-Open Fault Detection in CMOS Logic CircuitsNiraj K. Jha. TC, 37(4):426-432, 1988. On the design of robust multiple fault testable CMOS combinational logic circuitsSandip Kundu, Sudhakar M. Reddy, Niraj K. Jha. iccad 1988: 240-243 [doi]
The following publications are possibly variants of this publication: