Interleaving buffer insertion and transistor sizing into a single optimization

Yanbin Jiang, Sachin S. Sapatnekar, Cyrus Bamji, Juho Kim. Interleaving buffer insertion and transistor sizing into a single optimization. IEEE Trans. VLSI Syst., 6(4):625-633, 1998. [doi]

Authors

Yanbin Jiang

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Sachin S. Sapatnekar

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Cyrus Bamji

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Juho Kim

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