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Yanbin Jiang, Sachin S. Sapatnekar, Cyrus Bamji, Juho Kim. Interleaving buffer insertion and transistor sizing into a single optimization. IEEE Trans. VLSI Syst., 6(4):625-633, 1998. [doi]
Possibly Related PublicationsThe following publications are possibly variants of this publication: Combined transistor sizing with buffer insertion for timing optimizationYanbin Jiang, Sachin S. Sapatnekar, Cyrus Bamji, Juho Kim. cicc 1998: 605-608 [doi] Concurrent transistor sizing and buffer insertion by considering cost-delay tradeoffsJuho Kim, Cyrus Bamji, Yanbin Jiang, Sachin S. Sapatnekar. ispd 1997: 130-135 [doi]
The following publications are possibly variants of this publication: