The following publications are possibly variants of this publication:
- Design of Mixed-Voltage I/O Buffer by Using NMOS-Blocking TechniqueMing-Dou Ker, Shih-Lun Chen. jssc, 41(10):2324-2333, 2006. [doi]
- Design on new tracking circuit of I/O buffer in 0.13µm cell library for mixed-voltage applicationZi-Ping Chen, Che-Hao Chuang, Ming-Dou Ker. iscas 2006: [doi]
- Design of 2.5 V/5 V mixed-voltage CMOS I/O buffer with only thin oxide device and dynamic N-well bias circuitMing-Dou Ker, Chia-Sheng Tsai. iscas 2003: 97-100 [doi]
- Design of 2xVDD-tolerant mixed-voltage I/O buffer against gate-oxide reliability and hot-carrier degradationHui-Wen Tsai, Ming-Dou Ker. mr, 50(1):48-56, 2010. [doi]
- Overview on ESD protection design for mixed-voltage I/O interfaces with high-voltage-tolerant power-rail ESD clamp circuits in low-voltage thin-oxide CMOS technologyMing-Dou Ker, Wei-Jen Chang. mr, 47(1):27-35, 2007. [doi]
- Design on mixed-voltage-tolerant I/O interface with novel tracking circuits in a 0.13-µm CMOS technologyChe-Hao Chuang, Ming-Dou Ker. iscas 2004: 577-580
- A 800 Mbps and 12.37 ps Jitter Bidirectional Mixed-Voltage I/O Buffer With Dual-Path Gate-Tracking CircuitChua-Chin Wang, Chih-Lin Chen, Hsin-Yuan Tseng, Hsiao-Han Hou, Chun-Ying Juan. tcas, 60-I(1):116-124, 2013. [doi]