Automatic methodology for placing the guard rings into chip layout to prevent latchup in CMOS IC's - researchr publication authors

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Ming-Dou Ker, Hsin-Chin Jiang, Jeng-Jie Peng, Tzay-Luen Shieh. Automatic methodology for placing the guard rings into chip layout to prevent latchup in CMOS IC's. In Proceedings of the 2001 8th IEEE International Conference on Electronics, Circuits and Systems, ICECS 2001, Malta, September 2-5, 2001. pages 113-116, IEEE, 2001. [doi]

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