The following publications are possibly variants of this publication:
- New experimental methodology to extract compact layout rules for latchup prevention in bulk CMOS IC'sMing-Dou Ker, Wen-Yu Lo, Chung-Yu Wu. cicc 1999: 143-146 [doi]
- Toward an Automatic Code Layout MethodologyJoseph B. Manzano, Ziang Hu, Yi Jiang, Ge Gan, Hyo Jung Song, Jung-Gyu Park. iwomp 2008: 157-160 [doi]
- Anomalous latchup failure induced by on-chip ESD protection circuit in a high-voltage CMOS IC productI-Cheng Lin, Chih-Yao Huang, Chuan-Jane Chao, Ming-Dou Ker. mr, 43(8):1295-1301, 2003. [doi]
- Compact Layout Rule Extraction for Latchup Prevention in a 0.25-?m Shallow-Trench-Isolation Silicided Bulk CMOS ProcessMing-Dou Ker, Wen-Yu Lo, Tung-Yang Chen, Howard Tang, S. S. Chen, M.-C. Wang. isqed 2001: 267-272 [doi]