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Burhan Khurshid. Technology-Optimized Fixed-Point Bit-Parallel Multipliers for FPGAs. VLSI Signal Processing, 89(2):293-317, 2017. [doi]
Possibly Related PublicationsThe following publications are possibly variants of this publication: Technology optimised fixed-point bit-parallel multiplier for LUT-based FPGAsBurhan Khurshid, Roohie Naaz Mir. ijhpsa, 6(1):28-35, 2016. [doi] LUT based realization of fixed-point multipliers targeting state-of-art FPGAsBurhan Khurshid. dafes, 21(2):89-115, 2017. [doi]
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