The following publications are possibly variants of this publication:
- Adjustable Delay Buffer Allocation under Useful Clock Skew SchedulingJuyeon Kim, Taewhan Kim. tcad, 36(4):641-654, 2017. [doi]
- An optimal algorithm for allocation, placement, and delay assignment of adjustable delay buffers for clock skew minimization in multi-voltage mode designsKyoung-Hwan Lim, Taewhan Kim. aspdac 2011: 503-508 [doi]
- An Optimal Allocation Algorithm of Adjustable Delay Buffers and Practical Extensions for Clock Skew Optimization in Multiple Power Mode DesignsKyoung-Hwan Lim, Deokjin Joo, Taewhan Kim. tcad, 32(3):392-405, 2013. [doi]
- Mixed allocation of adjustable delay buffers combined with buffer sizing in clock tree synthesis of multiple power mode designsKitae Park, Geunho Kim, Taewhan Kim. date 2014: 1-4 [doi]
- Optimal utilization of adjustable delay clock buffers for timing correction in designs with multiple power modesJuyeon Kim, Deokjin Joo, Taewhan Kim. integration, 52:91-101, 2016. [doi]
- Clock buffer polarity assignment utilizing useful clock skews for power noise reductionDeokjin Joo, Taewhan Kim. aspdac 2016: 226-231 [doi]