Scalable Resonant Power Clock Generation for Adiabatic Logic Design - researchr publication authors

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Ragh Kuttappa, Leo Filippini, Nicholas Sica, Baris Taskin. Scalable Resonant Power Clock Generation for Adiabatic Logic Design. In IEEE Computer Society Annual Symposium on VLSI, ISVLSI 2021, Tampa, FL, USA, July 7-9, 2021. pages 338-342, IEEE, 2021. [doi]

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