Scalable Resonant Power Clock Generation for Adiabatic Logic Design - researchr publication related

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Ragh Kuttappa, Leo Filippini, Nicholas Sica, Baris Taskin. Scalable Resonant Power Clock Generation for Adiabatic Logic Design. In IEEE Computer Society Annual Symposium on VLSI, ISVLSI 2021, Tampa, FL, USA, July 7-9, 2021. pages 338-342, IEEE, 2021. [doi]

The following publications are possibly variants of this publication:

Comprehensive Low Power Adiabatic Circuit Design with Resonant Power ClockingRagh Kuttappa, Steven Khoa, Leo Filippini, Vasil Pano, Baris Taskin. iscas 2020: 1-5 [doi]

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