A 13-bit 160MS/s pipelined subranging-SAR ADC with low-offset dynamic comparator

Weitao Li, Fule Li, Jia Liu, HongYu Li, Zhihua Wang. A 13-bit 160MS/s pipelined subranging-SAR ADC with low-offset dynamic comparator. In IEEE Asian Solid-State Circuits Conference, A-SSCC 2017, Seoul, Korea (South), November 6-8, 2017. pages 225-228, IEEE, 2017. [doi]

Authors

Weitao Li

This author has not been identified. Look up 'Weitao Li' in Google

Fule Li

This author has not been identified. Look up 'Fule Li' in Google

Jia Liu

This author has not been identified. Look up 'Jia Liu' in Google

HongYu Li

This author has not been identified. Look up 'HongYu Li' in Google

Zhihua Wang

This author has not been identified. Look up 'Zhihua Wang' in Google