A 13-bit 160MS/s pipelined subranging-SAR ADC with low-offset dynamic comparator

Weitao Li, Fule Li, Jia Liu, HongYu Li, Zhihua Wang. A 13-bit 160MS/s pipelined subranging-SAR ADC with low-offset dynamic comparator. In IEEE Asian Solid-State Circuits Conference, A-SSCC 2017, Seoul, Korea (South), November 6-8, 2017. pages 225-228, IEEE, 2017. [doi]

@inproceedings{LiLLLW17,
  title = {A 13-bit 160MS/s pipelined subranging-SAR ADC with low-offset dynamic comparator},
  author = {Weitao Li and Fule Li and Jia Liu and HongYu Li and Zhihua Wang},
  year = {2017},
  doi = {10.1109/ASSCC.2017.8240257},
  url = {https://doi.org/10.1109/ASSCC.2017.8240257},
  researchr = {https://researchr.org/publication/LiLLLW17},
  cites = {0},
  citedby = {0},
  pages = {225-228},
  booktitle = {IEEE Asian Solid-State Circuits Conference, A-SSCC 2017, Seoul, Korea (South), November 6-8, 2017},
  publisher = {IEEE},
  isbn = {978-1-5386-3178-2},
}