2 718GOPS configurable spiking convolutional sparse coding processor in 40nm CMOS - researchr publication authors

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Chester Liu, Sung-gun Cho, Zhengya Zhang. 2 718GOPS configurable spiking convolutional sparse coding processor in 40nm CMOS. In IEEE Asian Solid-State Circuits Conference, A-SSCC 2017, Seoul, Korea (South), November 6-8, 2017. pages 233-236, IEEE, 2017. [doi]

This author has not been identified. Look up 'Chester Liu' in GoogleThis author has not been identified. Look up 'Sung-gun Cho' in GoogleThis author has not been identified. Look up 'Zhengya Zhang' in Google

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