Chester Liu, Sung-gun Cho, Zhengya Zhang. 2 718GOPS configurable spiking convolutional sparse coding processor in 40nm CMOS. In IEEE Asian Solid-State Circuits Conference, A-SSCC 2017, Seoul, Korea (South), November 6-8, 2017. pages 233-236, IEEE, 2017. [doi]
@inproceedings{LiuCZ17-3,
title = {2 718GOPS configurable spiking convolutional sparse coding processor in 40nm CMOS},
author = {Chester Liu and Sung-gun Cho and Zhengya Zhang},
year = {2017},
doi = {10.1109/ASSCC.2017.8240259},
url = {https://doi.org/10.1109/ASSCC.2017.8240259},
researchr = {https://researchr.org/publication/LiuCZ17-3},
cites = {0},
citedby = {0},
pages = {233-236},
booktitle = {IEEE Asian Solid-State Circuits Conference, A-SSCC 2017, Seoul, Korea (South), November 6-8, 2017},
publisher = {IEEE},
isbn = {978-1-5386-3178-2},
}