The following publications are possibly variants of this publication:
- A Simulator for Evaluating Redundancy Analysis Algorithms of Repairable Embedded MemoriesRei-Fu Huang, Jin-Fu Li, Jen-Chieh Yeh, Cheng-Wen Wu. mtdt 2002: 68 [doi]
- A Simulator for E aluating Redundancy Analysis Algorithms of Repairable Embedded MemoriesRei-Fu Huang, Jin-Fu Li, Jen-Chieh Yeh, Cheng-Wen Wu. iolts 2002: 262 [doi]
- Efficient built-in redundancy analysis for embedded memories with 2-D redundancyShyue-Kung Lu, Yu-Chen Tsai, Chih-Hsien Hsu, Kuo-Hua Wang, Cheng-Wen Wu. tvlsi, 14(1):34-42, 2006. [doi]