Yehia Massoud, Steve S. Majors, Tareq Bustami, Jacob White. Layout Techniques for Minimizing On-Chip Interconnect Self Inductance. In DAC. pages 566-571, 1998. [doi]
@inproceedings{MassoudMBW98,
title = {Layout Techniques for Minimizing On-Chip Interconnect Self Inductance},
author = {Yehia Massoud and Steve S. Majors and Tareq Bustami and Jacob White},
year = {1998},
doi = {10.1145/277044.277194},
url = {http://doi.acm.org/10.1145/277044.277194},
tags = {layout},
researchr = {https://researchr.org/publication/MassoudMBW98},
cites = {0},
citedby = {0},
pages = {566-571},
booktitle = {DAC},
}