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Peter M. Maurer. Two new techniques for unit-delay compiled simulation. IEEE Trans. on CAD of Integrated Circuits and Systems, 11(9):1120-1130, 1992. [doi]
Possibly Related PublicationsThe following publications are possibly variants of this publication: Two New Techniques for Compiled Multi-Delay Logic SimulationYun Sik Lee, Peter M. Maurer. dac 1992: 420-423 [doi] Techniques for Unit-Delay Compiled SimulationPeter M. Maurer, Zhicheng Wang. dac 1990: 480-484 [doi] Optimization of the Parallel Technique for Compiled Unit-Delay SimulationPeter M. Maurer. iccad 1990: 70-73
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