Simultaneous Gate and Interconnect Sizing for Circuit-Level Delay Optimization

Noel Menezes, Satyamurthy Pullela, Lawrence T. Pileggi. Simultaneous Gate and Interconnect Sizing for Circuit-Level Delay Optimization. In DAC. pages 690-695, 1995. [doi]

Authors

Noel Menezes

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Satyamurthy Pullela

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Lawrence T. Pileggi

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