Noel Menezes, Satyamurthy Pullela, Lawrence T. Pileggi. Simultaneous Gate and Interconnect Sizing for Circuit-Level Delay Optimization. In DAC. pages 690-695, 1995. [doi]
@inproceedings{MenezesPP95,
title = {Simultaneous Gate and Interconnect Sizing for Circuit-Level Delay Optimization},
author = {Noel Menezes and Satyamurthy Pullela and Lawrence T. Pileggi},
year = {1995},
doi = {10.1145/217474.217612},
url = {http://doi.acm.org/10.1145/217474.217612},
tags = {optimization},
researchr = {https://researchr.org/publication/MenezesPP95},
cites = {0},
citedby = {0},
pages = {690-695},
booktitle = {DAC},
}