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A Data-Driven Verilog-A ReRAM Model

Ioannis Messaris, Alexander Serb, Spyros Stathopoulos, Ali Khiat, Spyridon Nikolaidis, Themistoklis Prodromakis. A Data-Driven Verilog-A ReRAM Model. IEEE Trans. on CAD of Integrated Circuits and Systems, 37(12):3151-3162, 2018. [doi]

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