Hierarchical VLSI Fault Tracing by Successive Circuit Extraction from CAD Layout Data in the CAD-Linked EB Test System

Katsuyoshi Miura, Koji Nakamae, Hiromu Fujioka. Hierarchical VLSI Fault Tracing by Successive Circuit Extraction from CAD Layout Data in the CAD-Linked EB Test System. J. Electronic Testing, 10(3):255-269, 1997. [doi]

Abstract

Abstract is missing.