Arkadiy Morgenshtein, Eby G. Friedman, Ran Ginosar, Avinoam Kolodny. Unified Logical Effort - A Method for Delay Evaluation and Minimization in Logic Paths With RC Interconnect. IEEE Trans. VLSI Syst., 18(5):689-696, 2010. [doi]
@article{MorgenshteinFGK10,
title = {Unified Logical Effort - A Method for Delay Evaluation and Minimization in Logic Paths With RC Interconnect},
author = {Arkadiy Morgenshtein and Eby G. Friedman and Ran Ginosar and Avinoam Kolodny},
year = {2010},
doi = {10.1109/TVLSI.2009.2014239},
url = {http://dx.doi.org/10.1109/TVLSI.2009.2014239},
tags = {logic},
researchr = {https://researchr.org/publication/MorgenshteinFGK10},
cites = {0},
citedby = {0},
journal = {IEEE Trans. VLSI Syst.},
volume = {18},
number = {5},
pages = {689-696},
}