Arkadiy Morgenshtein, Eby G. Friedman, Ran Ginosar, Avinoam Kolodny. Unified Logical Effort - A Method for Delay Evaluation and Minimization in Logic Paths With RC Interconnect. IEEE Trans. VLSI Syst., 18(5):689-696, 2010. [doi]
No references recorded for this publication.
No citations of this publication recorded.