A layout-based schematic method for very high-speed CMOS cell design

F. Mu, C. Svensson. A layout-based schematic method for very high-speed CMOS cell design. IEEE Trans. VLSI Syst., 7(1):144-148, 1999. [doi]

@article{MuS99:1,
  title = {A layout-based schematic method for very high-speed CMOS cell design},
  author = {F. Mu and C. Svensson},
  year = {1999},
  doi = {10.1109/92.748214},
  url = {http://doi.ieeecomputersociety.org/10.1109/92.748214},
  tags = {rule-based, layout, C++, design},
  researchr = {https://researchr.org/publication/MuS99%3A1},
  cites = {0},
  citedby = {0},
  journal = {IEEE Trans. VLSI Syst.},
  volume = {7},
  number = {1},
  pages = {144-148},
}