Full-chip subthreshold leakage power prediction and reduction techniques for sub-0.18-/spl mu/m CMOS

Siva G. Narendra, Vivek De, Shekhar Borkar, Dimitri A. Antoniadis, Anantha P. Chandrakasan. Full-chip subthreshold leakage power prediction and reduction techniques for sub-0.18-/spl mu/m CMOS. J. Solid-State Circuits, 39(3):501-510, 2004. [doi]

Authors

Siva G. Narendra

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Vivek De

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Shekhar Borkar

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Dimitri A. Antoniadis

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Anantha P. Chandrakasan

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