Siva G. Narendra, Vivek De, Shekhar Borkar, Dimitri A. Antoniadis, Anantha P. Chandrakasan. Full-chip subthreshold leakage power prediction and reduction techniques for sub-0.18-/spl mu/m CMOS. J. Solid-State Circuits, 39(3):501-510, 2004. [doi]
@article{NarendraDBAC04,
title = {Full-chip subthreshold leakage power prediction and reduction techniques for sub-0.18-/spl mu/m CMOS},
author = {Siva G. Narendra and Vivek De and Shekhar Borkar and Dimitri A. Antoniadis and Anantha P. Chandrakasan},
year = {2004},
doi = {10.1109/JSSC.2003.821776},
url = {https://doi.org/10.1109/JSSC.2003.821776},
researchr = {https://researchr.org/publication/NarendraDBAC04},
cites = {0},
citedby = {0},
journal = {J. Solid-State Circuits},
volume = {39},
number = {3},
pages = {501-510},
}