The following publications are possibly variants of this publication:
- Design of a clock jitter reduction circuit using gated phase blending between self-delayed clock edgesKiichi Niitsu, Naohiro Harigai, Daiki Hirabayashi, Daiki Oki, Masato Sakurai, Osamu Kobayashi, Takahiro J. Yamaguchi, Haruo Kobayashi. aspdac 2013: 103-104 [doi]
- A clock jitter reduction circuit using gated phase blending between self-delayed clock edgesKiichi Niitsu, Naohiro Harigai, Daiki Hirabayashi, Daiki Oki, Masato Sakurai, Osamu Kobayashi, Takahiro J. Yamaguchi, Haruo Kobayashi. vlsic 2012: 142-143 [doi]