Highly Reliable Reference Bitline Bias Designs for 64 Mb and 128 Mb Chain FeRAMs

Ryu Ogiwara, Daisaburo Takashima, Sumiko Doumae, Shinichiro Shiratake, Ryosuke Takizawa, Hidehiro Shiga. Highly Reliable Reference Bitline Bias Designs for 64 Mb and 128 Mb Chain FeRAMs. J. Solid-State Circuits, 50(5):1324-1331, 2015. [doi]

@article{OgiwaraTDSTS15,
  title = {Highly Reliable Reference Bitline Bias Designs for 64 Mb and 128 Mb Chain FeRAMs},
  author = {Ryu Ogiwara and Daisaburo Takashima and Sumiko Doumae and Shinichiro Shiratake and Ryosuke Takizawa and Hidehiro Shiga},
  year = {2015},
  doi = {10.1109/JSSC.2015.2405932},
  url = {http://dx.doi.org/10.1109/JSSC.2015.2405932},
  researchr = {https://researchr.org/publication/OgiwaraTDSTS15},
  cites = {0},
  citedby = {0},
  journal = {J. Solid-State Circuits},
  volume = {50},
  number = {5},
  pages = {1324-1331},
}