The following publications are possibly variants of this publication:
- A 5-Gb/s/pin Transceiver for DDR Memory Interface With a Crosstalk Suppression SchemeKwang-Il Oh, Lee-Sup Kim, Kwang-Il Park, Young-Hyun Jun, Joo-Sun Choi, Kinam Kim. jssc, 44(8):2222-2232, 2009. [doi]
- A 5-Gb/s/pin transceiver for DDR memory interface with a crosstalk suppression schemeKwang-Il Oh, Lee-Sup Kim, Kwang-Il Park, Young-Hyun Jun, Kinam Kim. cicc 2008: 639-642 [doi]
- A Built-In Self-Test scheme for DDR memory output timing test and measurementHyunjin Kim, Jacob A. Abraham. vts 2012: 7-12 [doi]