Buffer/flip-flop block planning for power-integrity-driven floorplanning - researchr publication authors

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Hsin-Hua Pan, Hung-Ming Chen, Chia-Yi Chang. Buffer/flip-flop block planning for power-integrity-driven floorplanning. In 10th International Symposium on Quality of Electronic Design (ISQED 2009), 16-18 March 2009, San Jose, CA, USA. pages 488-493, IEEE, 2009. [doi]

This author has not been identified. Look up 'Hsin-Hua Pan' in GoogleThis author has not been identified. Look up 'Hung-Ming Chen' in GoogleThis author has not been identified. Look up 'Chia-Yi Chang' in Google

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