Hsin-Hua Pan, Hung-Ming Chen, Chia-Yi Chang. Buffer/flip-flop block planning for power-integrity-driven floorplanning. In 10th International Symposium on Quality of Electronic Design (ISQED 2009), 16-18 March 2009, San Jose, CA, USA. pages 488-493, IEEE, 2009. [doi]
@inproceedings{PanCC09,
title = {Buffer/flip-flop block planning for power-integrity-driven floorplanning},
author = {Hsin-Hua Pan and Hung-Ming Chen and Chia-Yi Chang},
year = {2009},
doi = {10.1109/ISQED.2009.4810343},
url = {http://dx.doi.org/10.1109/ISQED.2009.4810343},
researchr = {https://researchr.org/publication/PanCC09},
cites = {0},
citedby = {0},
pages = {488-493},
booktitle = {10th International Symposium on Quality of Electronic Design (ISQED 2009), 16-18 March 2009, San Jose, CA, USA},
publisher = {IEEE},
}