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Joonseok Park, Pedro C. Diniz, K. R. Shesha Shayee. Performance and Area Modeling of Complete FPGA Designs in the Presence of Loop Transformations. IEEE Transactions on Computers, 53(11):1420-1435, 2004. [doi]
Possibly Related PublicationsThe following publications are possibly variants of this publication: Performance and Area Modeling of Complete FPGA Designs in the presence of Loop TransformationsK. R. Shesha Shayee, Joonseok Park, Pedro C. Diniz. fccm 2003: 296 [doi] Performance and Area Modeling of Cmplete FPGA Designs in the Presence of Loop TransformationsK. R. Shesha Shayee, Joonseok Park, Pedro C. Diniz. fpl 2003: 313-323 [doi]
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