The following publications are possibly variants of this publication:
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- A 3-bit/2UI 27Gb/s PAM-3 Single-Ended Transceiver Using One-Tap DFE for Next-Generation Memory InterfaceHyunsu Park, Junyoung Song, Yeonho Lee, Jincheol Sim, Jonghyuck Choi, Chulwoo Kim. isscc 2019: 382-384 [doi]
- A 20-Gb/s/Pin Compact Single-Ended DCC-Less DECS Transceiver With CDR-Less RX Front-End for On-Chip LinksJaeyoung Seo, Sooeun Lee, Myungguk Lee, Changjae Moon, Byungsub Kim. jssc, 58(11):3253-3265, November 2023. [doi]
- A 25-Gb/s Single-Ended PAM-4 Receiver With Time-Windowed LSB Decoder for High-Speed Memory InterfacesYoonjae Choi, Hyunsu Park, Jonghyuck Choi, Jincheol Sim, Youngwook Kwon, Seungwoo Park, Seongcheol Kim, Changmin Sim, Chulwoo Kim. jssc, 58(7):2005-2015, 2023. [doi]
- A 1.1 mW/Gb/s 10 Gbps half-rate clock-embedded transceiver for high-speed links in 65 nm CMOSKyongsu Lee, Youngjin Kim, Kyung-Sub Son, Sangmin Lee, Jin-Ku Kang. ieiceee, 11(17):20140671, 2014. [doi]
- A 0.64-pJ/Bit 28-Gb/s/Pin High-Linearity Single-Ended PAM-4 Transmitter With an Impedance-Matched Driver and Three-Point ZQ Calibration for Memory InterfaceYong-Un Jeong, Hyunkyu Park, Changho Hyun, Joo-Hyung Chae, Shin-Hyun Jeong, Suhwan Kim. jssc, 56(4):1278-1287, 2021. [doi]
- 22.4 A 32Gb/s Digital-Intensive Single-Ended PAM-4 Transceiver for High-Speed Memory Interfaces Featuring a 2-Tap Time-Based Decision Feedback Equalizer and an In-Situ Channel-Loss MonitorPo-Wei Chiu, Chris H. Kim. isscc 2020: 336-338 [doi]