Zhenlin Pei, Mahta Mayahinia, Hsiao-Hsuan Liu, Mehdi B. Tahoori, Francky Catthoor, Zsolt Tokei, Chenyun Pan. Technology/Memory Co-Design and Co-Optimization Using E-Tree Interconnect. In Himanshu Thapliyal, Ronald F. DeMara, Inna Partin-Vaisband, Srinivas Katkoori, editors, Proceedings of the Great Lakes Symposium on VLSI 2023, GLSVLSI 2023, Knoxville, TN, USA, June 5-7, 2023. pages 159-162, ACM, 2023. [doi]
Abstract is missing.