Harold Pilo, Igor Arsovski, Kevin Batson, Geordie Braceras, John Gabric, Robert M. Houle, Steve Lamphier, Frank Pavlik, Adnan Seferagic, Liang-Yu Chen, Shang-Bin Ko, Carl Radens. A 64Mb SRAM in 32nm High-k metal-gate SOI technology with 0.7V operation enabled by stability, write-ability and read-ability enhancements. In IEEE International Solid-State Circuits Conference, ISSCC 2011, Digest of Technical Papers, San Francisco, CA, USA, 20-24 February, 2011. pages 254-256, IEEE, 2011. [doi]
@inproceedings{PiloABBGHLPSCKR11,
title = {A 64Mb SRAM in 32nm High-k metal-gate SOI technology with 0.7V operation enabled by stability, write-ability and read-ability enhancements},
author = {Harold Pilo and Igor Arsovski and Kevin Batson and Geordie Braceras and John Gabric and Robert M. Houle and Steve Lamphier and Frank Pavlik and Adnan Seferagic and Liang-Yu Chen and Shang-Bin Ko and Carl Radens},
year = {2011},
doi = {10.1109/ISSCC.2011.5746307},
url = {http://dx.doi.org/10.1109/ISSCC.2011.5746307},
researchr = {https://researchr.org/publication/PiloABBGHLPSCKR11},
cites = {0},
citedby = {0},
pages = {254-256},
booktitle = {IEEE International Solid-State Circuits Conference, ISSCC 2011, Digest of Technical Papers, San Francisco, CA, USA, 20-24 February, 2011},
publisher = {IEEE},
isbn = {978-1-61284-303-2},
}